About this role
Lead ASIC/FPGA Design Engineer at Aalyria. Location: Livermore, California, United States. Role: design RTL, verify RTL, coordinate integration Requirements: Lead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route Certifications: security clearance Commitment: Full Time Workplace: Onsite Languages: English