About this role
Technical Lead Design Verification Engineer at Astera Labs. Location: San Jose, California, United States. Role: plan verification, write tests, debug failures Requirements: Bachelor in Electrical Engineering required; Masters preferred; 5+ years in verifying complex SoCs for server/storage/networking; SystemVerilog/UVM/C/C++ expertise; scripting (Python/Perl); ability to plan, write tests, and debug; authorized to work in the US. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, C, C++, Python, Perl, simulators, regression systems, Verification IPs Commitment: Full Time Workplace: Onsite Languages: English