About this role
Technical Lead Design Verification Engineer at Astera Labs. Location: San Jose, California, United States. Role: verify designs, write tests, debug failures Requirements: Bachelor’s in Electrical Engineering; 5+ years in verifying complex SoCs for server/storage/networking; strong problem-solving; US work-authorized; able to work with minimal supervision. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, C, C++, Python Commitment: Full Time Workplace: Onsite Languages: English