About this role
Lead Design Verification Engineer at Altera. Location: Hyderabad or Bengaluru or Penang. Role: verifying FPGA, developing test-benches, collaborating with teams Requirements: BS/MS/PhD in Electrical or Computer Science Engineering with 8+ years of experience in pre-silicon verification; experience with OVM/UVM, SystemVerilog, constrained random verification. Category: Engineering Seniority: Senior Level Tools: OVM, UVM, SystemVerilog, constrained random verification Commitment: Full Time Workplace: Onsite Languages: English