About this role
Technical Lead, Design Verification at Marvell. Location: Santa Clara, California, United States. Role: Develop verification, Lead testbenches, Collaborate cross-team Requirements: Lead verification for SoCs, develop UVM environments, mentor engineers, strong SystemVerilog, Python, ARM/NoC expertise. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Python, Xcelium, Questa, VCS Commitment: Full Time Workplace: Onsite Languages: English