About this role
RTL Design Lead at Erbits Private Limited. Location: Noida, Uttar Pradesh, India. Role: Lead design, Collaborate teams, Mentor engineers Requirements: Lead RTL design for ASIC/SoC projects; strong Verilog/SystemVerilog; AMBA protocols; flow including synthesis, lint, CDC, low-power; debug and mentor engineers. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, AMBA protocols, Synthesis, Lint, CDC, Low-power design Commitment: Full Time Workplace: Onsite Languages: English