About this role
Lead Design Engineer at Cadence. Location: San Jose, California, United States. Role: lead validation, design testing, automate reporting Requirements: Lead DDR validation, testing, data analysis, and cross-team collaboration; 4+ years (M.Tech) or 6+ years (B.Tech) in relevant field. Category: Engineering Seniority: Mid Level Tools: Python, JIRA, DDR5, LPDDR5, HBM4, GDDR7, DDR interfaces Commitment: Full Time Workplace: Onsite Languages: English