About this role
Principal Member of the Technical Staff - IP Engineering at Globalfoundries. Location: Hsinchu, /, Taiwan. Role: leading development, mentoring teams, driving execution Requirements: Master's in EE/CS or related, 15+ years in digital front-end/RTL/verification or computational IP with technical leadership; proficiency in SystemVerilog, Verilog, UVM, C/C++, Python, Perl; experience leading distributed teams. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, UVM, C/C++, Python, Perl Commitment: Full Time Workplace: Onsite Languages: English