About this role
Lead Design Engineer at Cadence. Location: San Jose, California, United States. Role: designing components, performing simulation, validating measurements Requirements: Master's in EE/CS,5+ years relevant experience,expertise in high-speed interconnects,signal integrity,lab validation and simulation,proficiency with PCB/packaging concepts and test equipment. Category: Engineering Seniority: Senior Level Tools: Oscilloscope, Vector Network Analyzer (VNA), Function Generator, Spectrum Analyzer Commitment: Full Time Workplace: Hybrid Languages: English