About this role
Senior Design Verification Engineer at Viasat, Inc.. Location: Tempe or Independence or Arizona or Ohio or San Jose or New York City. Role: architecting environments, developing testbench, debugging tests Requirements: 8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%. Category: Engineering Seniority: Senior Level Tools: UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira Certifications: secret clearance Commitment: Full Time Workplace: Hybrid Languages: English