About this role
RTL Silicon Design Engineer at Advanced Micro Devices, Inc. Location: Hyderabad, Telangana, India. Role: developing rtl, resolving regressions, mentoring designers Requirements: Proficient in Verilog/System Verilog and front-end RTL flows for ASIC/IP; experience with networking protocols, EDA tools, AI-assisted coding, scripting (Python/Perl/TCL/csh/bash); Bachelors/Masters in CE/EE and ~8 years RTL experience preferred. Category: Engineering Seniority: Senior Level Tools: Verilog, System Verilog, VS Code, GitHub Copilot, Cursor, Claude, Codex, GPT, Microsoft M365 Copilot, ChatGPT, Atlassian Rovo, Python, Perl, TCL, Makefile, csh, bash, Synopsys, Cadence, Siemens, AXI, AHB, AMBA, MACsec, IPsec Commitment: Full Time Workplace: Onsite Languages: English