About this role
Staff Engineer, Design Verification at Renesas Electronics. Location: Bengaluru, Karnataka, India. Role: defining strategy, developing environments, mentoring engineers Requirements: Bachelor's or Master's in electronics,5-12 years in SoC/IP verification, strong UVM/SystemVerilog/SVA skills, metric-driven coverage closure, experience with directed/constrained-random methods, Verilog,C/C++, scripting and AI/ML-assisted verification preferred. Category: Engineering Seniority: Senior Level Tools: UVM, SystemVerilog, SVA, Verilog, C, C++, Shell, Python, Perl, TCL, AI/ML, Gate-Level Simulation (GLS) Commitment: Full Time Workplace: Hybrid Languages: English