About this role
Director, Silicon Design Engineering at Intel. Location: Santa Clara or Austin or Hillsboro. Role: performing timing, optimizing timing, collaborating teams Requirements: Requires 6–12+ years timing/physical design experience, BS in EE/CE (or equivalent), proficiency in static timing analysis, timing constraint generation, SoC clocking, TCL scripting, and collaboration with cross-functional teams. Category: Engineering Seniority: Senior Level Tools: TCL, TFM, EDA tools Commitment: Full Time Workplace: Hybrid Languages: English