About this role
SMTS, Design Rule Enablement Team TPG at Micron Technology, Inc.. Location: Hiroshima, Hiroshima Prefecture, Japan. Role: leading enablement, defining rules, managing structures Requirements: MS/PhD in EE/microelectronics/physics, 15+ years semiconductor experience (process integration/PDK/yield/design), expertise in DRAM design rules and test structures, Cadence & Siemens tool familiarity, and experience coordinating cross-functional teams. Category: Engineering Seniority: Senior Level Tools: Cadence, Siemens, LLMs, GenAI Commitment: Full Time Workplace: Onsite Languages: English