About this role
Senior Staff RTL Design Engineer at Synopsys. Location: Bengaluru, Karnataka, India. Role: design RTL, build testbenches, drive timing Requirements: Bachelor's in Electrical Engineering with 8+ years of hands-on ASIC/IP design, or Master's with 6+ years; strong RTL/Verilog/SystemVerilog, multi-site collaboration, high-speed IP design experience. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, Verilog-AMS, Scripting (Perl or Shell), Static Timing Analysis, Synthesis, Lint, CDC, Formal Verification, Perforce Commitment: Full Time Workplace: Onsite Languages: English