About this role
Senior Engineer II - Design at Microchiphr. Location: Hyderabad, Telangana, India. Role: Designs reference, Develop RTL, Validate designs Requirements: Design FPGA reference designs; RTL development; timing closure; FPGA I/O bring-up; cross-functional collaboration. Category: Engineering Seniority: Senior Level Tools: Verilog, RTL, FPGA, PCIe, Gigabit Ethernet, DDR, JESD204B/C, Oscilloscopes Commitment: Full Time Workplace: Onsite Languages: English