About this role
Principal Layout Designer at Microchip Technology Inc. Location: Chandler, Arizona, United States. Role: developing blocks, verifying physicals, optimizing layout Requirements: 10+ years custom analog CMOS layout experience, knowledge of advanced CMOS processes (28nm and below), experience with Cadence/Pegasus/Calibre, strong physical verification and problem-solving skills. Category: Engineering Seniority: Senior Level Tools: Cadence, Pegasus, Calibre, Cadence SKILL Commitment: Full Time Workplace: Onsite Languages: English