About this role
Digital Designer - FPGA & Video Rendering at SeeCubic. Location: Eindhoven, North Brabant, Netherlands. Role: developing ip, designing solutions, verifying designs Requirements: Bachelor's in EE/CS or similar, 3+ years FPGA video processing experience, HLS experience (Catapult preferred), TCL scripting, timing and multi-clock design, knowledge of on/off-chip protocols, strong documentation and verification skills. Category: Engineering Seniority: Mid Level Tools: High-Level Synthesis (HLS), Catapult HLS, Vitis, HDL Coder, TCL, Quartus, Vivado, AXI-4, Avalon, SPI, I²C Commitment: Full Time Workplace: Onsite Languages: English