About this role
FPGA design FADEC SPU at Scalian. Location: San Diego, California, United States. Role: Designing, Verifying, Implementing Requirements: FPGAs design experience; FADEC SPU familiarity; mid-senior level with full-time employment. Category: Engineering Seniority: Mid Level Tools: FPGA, VHDL/Verilog, Embedded Systems, CAD Tools, Simulation Tools, DSP Commitment: Full Time, Contract, Internship, Temporary, Seasonal, Volunteer Workplace: Onsite Languages: English