About this role
Scientist (Multi Chiplet Heterogeneous Integration and High speed IO designer (SIP)), IME at ASTARPRD. Location: Singapore. Role: developing pdk, modelling interconnects, collaborating teams Requirements: PhD in Electrical or Computer Engineering with 5+ years PDK and multi-physics modelling experience; programming/scripting in SKILL, ADL, Python, Perl, C/C++, TCL, or AEL; familiarity with AI/ML and reduced-order models. Category: Research and Development (R&D) Seniority: Senior Level Tools: SKILL, ADL, Python, Perl, C/C++, TCL, AEL Commitment: Full Time Workplace: Onsite Languages: English