About this role
ASIC Design Engineer at Hewlett Packard Enterprise. Location: Sunnyvale, California, United States. Role: design module, implement RTL, verify design Requirements: Design ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams. Category: Engineering Seniority: Mid Level Tools: Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python Commitment: Full Time Workplace: Onsite Languages: English