About this role
Senior Frontend PHY IC Design Engineer (DSP focus) at Morse Micro. Location: Sydney, New South Wales, Australia. Role: Designing, Verifying, Bringing up Requirements: Design, verification and bring-up of IEEE 802.11ah PHY; 3+ years DSP/PHY IC design; RTL/SystemVerilog; Python; Linux; BSc/MSc/PhD in EE/EC/CS; low-power, multi-clock design. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog-A, C, Python, Matlab, RTL simulators, AMS simulators, Cadence, Synopsys, Linux Commitment: Full Time Workplace: Onsite Languages: English