About this role
Mixed Signal Design Engineer at Melexis. Location: Bevaix, Neuchâtel, Switzerland. Role: verifying design, developing models, performing simulation Requirements: Master's in electronic/microelectronic engineering, 2+ years verification/design experience in microelectronics, knowledge of SystemVerilog/UVM and Linux scripting (Shell, Python), effective English communication. Category: Engineering Seniority: Entry Level Tools: SystemVerilog, UVM, Shell, Python, Linux Commitment: Full Time Workplace: Onsite Languages: English