About this role
Senior Principal Design Verification Engineer at onsemi. Location: Bengaluru, Karnataka, India. Role: defining strategy, developing environments, debugging rtl Requirements: 13+ years digital verification experience; BS/MS in Electrical Engineering or related field; expertise in UVM/SystemVerilog, constrained-random and assertion-based verification, coverage-driven verification, and mentoring/leading verification teams. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Python, C++, SystemRDL, IP-XACT, Electronic Medical Records (EMR) Commitment: Full Time Workplace: Onsite Languages: English