About this role
Principal Design Engineer at Cadence. Location: Austin, Texas, United States. Role: designing components, leading verification, supporting customers Requirements: Bachelor's in engineering,7+ years experience in design/verification,UVM and SVA experience,verification planning,test development,debugging,functional coverage analysis. Category: Engineering Seniority: Senior Level Tools: Universal Verification Methodology (UVM), System Verilog Assertions (SVA) Commitment: Full Time Workplace: Hybrid Languages: English