About this role
Design Engineer I at Silabs. Location: Austin, Texas, United States. Role: implementing designs, analyzing timing, maintaining constraints Requirements: Master's in EE/CE or related; experience with static timing analysis, timing constraints (SDC), digital IC implementation and signoff; strong analytical and communication skills; familiarity with Linux/Unix and EDA tool flows; scripting with Python/Perl/Tcl a plus. Category: Engineering Seniority: Entry Level Tools: Static Timing Analysis (STA), SDC, Cadence Tempus, Synopsys PrimeTime, Python, Perl, Tcl, Linux/Unix, EDA, RTL, GDSII Commitment: Full Time Workplace: Hybrid Languages: English