About this role
Senior FPGA Design Engineer (Nextest, San Jose, CA) at Teradyne Inc. Location: San Jose, California, United States. Role: architecting solutions, implementing designs, mentoring engineers Requirements: Design and implement FPGA solutions; Verilog, C/C++, Altera/AMD tool flow experience; static timing analysis, transceiver and DRAM/Flash interface experience; bachelor’s (5+ yrs) or master’s (3+ yrs) in EE. Category: Engineering Seniority: Senior Level Tools: C, C++, Verilog, Altera/AMD FPGA tool flows, UVM, Linux, Windows Commitment: Full Time Workplace: Onsite Languages: English