About this role
Ingeniero/a Senior de FPGAs - FCAS at Grupo Oesía. Location: Rivas-Vaciamadrid, Madrid, Spain. Role: Design FPGA, Integrate IPs, Verify HDL Requirements: Senior FPGA engineer with 5+ years in FPGA design for embedded high-performance systems; RTL design in VHDL/SystemVerilog; IP core integration; HDL simulation/verification; embedded SoC/MPSoC knowledge; English business proficiency. Category: Engineering Seniority: Senior Level Tools: Libero, PolarFire IPs, Place & Route, ModelSim, Questa, Riviera-PRO Commitment: Full Time Workplace: Hybrid Languages: English, Spanish