About this role
Mixed Signal Logic Design Engineer at Intel. Location: Bangalore, Karnataka, India. Role: defining microarchitecture, implementing rtl, reviewing verification Requirements: Bachelor's or Master's in ECE/Computer Engineering, 3–4+ years experience, System Verilog RTL, low-power design (UPF, clock gating), Spyglass/VC Lint/CDC, VCS/Verdi, scripting (Perl/Python/TCL). Category: Engineering Seniority: Mid Level Tools: System Verilog, UPF, Spyglass, VC Lint, CDC, VCS, Verdi, Perl, Python, TCL Commitment: Full Time Workplace: Hybrid Languages: English