About this role
Senior Memory Systems Design Engineer - FPGA ( 5-8 Years) at Sandisk. Location: Bengaluru, Karnataka, India. Role: designing FPGA, developing RTL, validating systems Requirements: 5+ years FPGA and RTL experience with Xilinx FPGAs, VHDL/Verilog, embedded C/C++, high-speed interfaces (PCIe, DDR, NAND), and system validation skills. Category: Engineering Seniority: Senior Level Tools: Xilinx FPGAs, Zynq, UltraScale+, Versal, Vivado Design Suite, IP Integrator, VHDL, Verilog, PCIe, AXI4, DDR3, DDR4, NAND Flash, Zynq SoCs, ChipScope, ILA, Git, SVN, Python, Tcl, Bash, C, C++, High-Level Synthesis (HLS) Commitment: Full Time Workplace: Onsite Languages: English