About this role
Design and Verification Engineer at ChipAgents. Location: San Jose, California, United States. Role: modeling workflows, designing RTL, building testbenches Requirements: Degree in EE/CE or related, experience in RTL design and functional verification, proficiency with Verilog/SystemVerilog, UVM, and simulation tools; strong collaboration and AI/ML interest preferred. Category: Engineering Seniority: Mid Level Tools: Verilog/SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Siemens Questa, Microsoft Excel Commitment: Full Time Workplace: Onsite Languages: English