About this role
Senior RTL Design Engineer – DDR/LPDDR Memory Controller at Advanced Micro Devices, Inc. Location: Austin or Boxborough or Vancouver. Role: developing rtl, optimizing designs, collaborating verification Requirements: Experience in digital design, Verilog/SystemVerilog, scripting (Python/Perl/Tcl), EDA tool flows, and DDR/LPDDR memory systems; bachelor’s or master’s in related field and strong communication and problem-solving skills. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, Python, Perl, Tcl, EDA tools Commitment: Full Time Workplace: Hybrid Languages: English