About this role
Digital Verification Engineer at Qblox. Location: Delft, Zuid-Holland, Netherlands. Role: owning verification, developing testbenches, collaborating teams Requirements: 4+ years RTL verification experience; fluent in SystemVerilog/UVM and Python; experience with simulators (Cadence Xcelium, Synopsys VCS), VHDL, Git; strong verification planning and testbench development skills. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, Python, Cadence Xcelium, Synopsys VCS, VHDL, AMBA AXI, Avalon, Git, Cocotb, PyUVM, GitLab, Docker, Podman, C, C++ Commitment: Full Time Workplace: Hybrid Languages: English