About this role
Senior Physical Design Engineer at Tenstorrent. Location: Tokyo, Tokyo, Japan. Role: Lead chiplet and chip-top implementation, Own chip-top floorplanning and integration, Drive full physical verification and convergence Requirements: Senior physical design engineer with 10+ years in SoC/ASIC/CPU/GPUs, proficient with Synopsys/Cadence, TCL and Python, and able to mentor teammates. Category: Engineering Seniority: Senior Level Tools: Synopsys, Cadence, TCL, Python Commitment: Full Time Workplace: Hybrid Languages: English