About this role
Principal Engineer, ASIC Design Verification at Ayar Labs. Location: Bengaluru, Karnataka, India. Role: Define testbenches, Lead verification, Mentor engineers Requirements: MS in Electrical/Computer Engineering; 12+ years in ASIC/SoC verification; SystemVerilog/UVM expert; proven verification environment development; strong scripting; knowledge of PCIe/AMBA/UCIe; leadership and mentoring experience. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Python, Perl, Tcl, Shell Commitment: Full Time Workplace: Onsite Languages: English