About this role
Senior Design Engineer-CPU at NextSilicon. Location: Giv'atayim, Tel Aviv District, Israel. Role: driving design, coordinating teams, monitoring progress Requirements: 6+ years ASIC experience, VLSI expertise, design-for-timing and power skills, experience with front-end flows (CDC, LINT, Synthesis), FPGA exposure; strong interpersonal and leadership abilities; high-frequency/CPU design is a plus. Category: Engineering Seniority: Senior Level Tools: RISC-V, CDC, LINT, Synthesis, FPGA Commitment: Full Time Workplace: Onsite Languages: English