About this role
Sr. Principal Engineer, RTL ASIC Design at Marvell. Location: Hyderabad, Telangana, India. Role: defining architecture, implementing rtl, driving verification Requirements: Requires 16–18+ years of experience, degree in CS or EE, expertise in SoC architecture, RTL/HDL, ARM-based designs, high-speed interfaces (PCIe/CXL/DDR), VLSI flow, scripting, performance analysis, and strong collaboration skills. Category: Engineering Seniority: Senior Level Tools: PCIe, CXL, DDR, ARM, HDL, VLSI Commitment: Full Time Workplace: Onsite Languages: English