About this role
Design Engineer at Cadence. Location: Austin, Texas, United States. Role: designing components, verifying functionality, developing tests Requirements: Master's in Computer/Electrical Engineering or related field; experience in design/functional verification, UVM, SVA, AMBA, AI/ML for verification; test plan and environment development skills. Category: Engineering Seniority: Mid Level Tools: Universal Verification Methodology (UVM), System Verilog Assertions (SVA), Advanced Microcontroller Bus Architecture (AMBA), Artificial Intelligence (AI), Machine Learning (ML) Commitment: Full Time Workplace: Hybrid Languages: English