About this role
Digital Verification Development Engineer at Silvaco. Location: Cairo, Cairo Governorate, Egypt. Role: developing testplan, writing stimulus, analyzing coverage Requirements: Bachelor's in Electronics or Computer Engineering; 0-3 years developing SystemVerilog/UVM verification environments; strong Verilog/SystemVerilog skills; Unix/Linux proficiency; coverage and scripting familiarity. Category: Engineering Seniority: No Prior Experience Required Tools: SystemVerilog, Verilog, UVM, Unix, Linux, Shell, Perl, TCL, FPGA Commitment: Full Time Workplace: Onsite Languages: English