About this role
RTL Design Engineer at AMD. Location: Markham or Vancouver. Role: designing RTL, mentoring engineers, integrating subsystems Requirements: RTL and micro-architecture expertise for complex digital IP; Verilog/SystemVerilog, VCS, lint/synthesis/STA flows, scripting (Perl/Shell), EE degree required; strong debugging and problem-solving. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, VCS, Perl, Shell, Lint, CDC/RDC, synthesis, LEC, STA, DFx, DFT, DFD, AI Commitment: Full Time Workplace: Hybrid Languages: English