About this role
Senior Verification Engineer at Blaize. Location: Hyderabad, Telangana, India. Role: verify IP, develop testbench Requirements: 5-8 years hands-on IP/SoC/ASIC verification; strong SystemVerilog/UVM; AMBA/JTAG knowledge; scripting with Perl/Python; memory/subsystem understanding. Category: Engineering Seniority: Senior Level Tools: UVM, SystemVerilog, AMBA, JTAG, Perl, Python Commitment: Full Time Workplace: Onsite Languages: English