About this role
Senior FPGA Design Engineer,( Nextest, San Jose, CA) at Teradyne Inc. Location: San Jose, California, United States. Role: architecting solutions, implementing designs, mentoring engineers Requirements: B.S. or M.S. in Electrical Engineering, 8+ years relevant experience, RTL/Verilog, FPGA transceiver and timing experience, C/C++, EM/FPGA tool flow familiarity, lab equipment experience. Category: Engineering Seniority: Senior Level Tools: C, C++, Linux, Windows, Verilog HDL, Intel FPGA tool flows, Xilinx FPGA tool flows, UVM, ATE Commitment: Full Time Workplace: Onsite Languages: English