About this role
Layout Design, Staff Engineer at Synopsys. Location: Ho Chi Minh City, Ho Chi Minh City, Vietnam. Role: designing layout, debugging violations, collaborating teams Requirements: 5+ years custom IC layout experience focused on memory, standard cells, or analog/mixed-signal; Bachelor’s or Master’s in electronics/telecom/physics; proficiency with Cadence Virtuoso, Synopsys Custom Compiler, Calibre DRC/LVS; strong DRC/LVS debugging and documentation skills. Category: Engineering Seniority: Senior Level Tools: Cadence Virtuoso Layout Suite, Synopsys Custom Compiler, Calibre DRC/LVS Commitment: Full Time Workplace: Onsite Languages: English