About this role
Interconnect Design Engineer at Sifive. Location: Santa Clara or Cambridge or Austin or Boston. Role: designing interconnect, implementing generators, integrating ip Requirements: Expertise in interconnect, cache/coherency and RTL generator design; strong software engineering and hardware RTL skills; BS/MS in EE/CE/CS or equivalent experience. Category: Engineering Seniority: Senior Level Tools: Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Bluespec, Git, Github, Jira, Confluence, TileLink, RISC-V, AXI, AHB, APB, CHI Commitment: Full Time Workplace: Onsite Languages: English