About this role
Digital Front-End Design Engineer – Drive the complete RTL-to-GDS flow and shape next-generation silicon solutions. What you will do As a Digital Front-End Design Engineer, you are responsible for all design tasks in the RTL-to-GDS flow, ensuring high-quality and efficient implementation of complex ASIC designs. You work within a highly skilled Front-End (FE) team that provides design services to both internal IMEC research groups and external customers worldwide. The team consists of 10 members with diverse experience levels, offering a collaborative environment for knowledge sharing and technical growth. Perform RTL synthesis and optimize timing, area, and power. Execute DFT (Design-for-Test) insertion using industry-standard tools. Conduct Logical Equivalence Checking (LEC) to validate design integrity. Generate and validate ATPG (Automatic Test Pattern Generation) patterns. Improve test coverage through advanced methodologies. Run pre-layout and post-layout test pattern simulations to ensure robustness. Collaborate closely with physical design teams for seamless RTL-to-GDS integration. Utilize Cadence/Synopsys EDA tools for synthesis, DFT insertion, and ATPG. Apply Tessent (Siemens) tools for DFT insertion and ATPG in specific projects. Troubleshoot and resolve design issues across the front-end flow. Document design processes and contribute to continuous improvement initiatives. Engage with internal and external stakeholders to deliver high-quality design services. You are an ASIC design professional with a strong interest in front-end methodologies and a passion for delivering high-quality silicon. You bring: 0-2 years of experience in ASIC front-end design, including RTL-to-Netlist flow. A master’s degree in a related field (electrical or computer engineering) is required for candidates with no industry experience. Expertise in synthesis, DFT, LEC, ATPG, and test coverage improvement. Hands-on experience with Cadence (preferred) (Genus, Modus, Conformal, Xcelium, etc.) and/or Synopsys toolsets (DC, FC, TestMAX, SpyGlass, etc.). Familiarity with Tessent tools for DFT and ATPG. Understanding of and strong interest in digital design principles, timing closure, and test strategies. Proficiency in Verilog/SystemVerilog and scripting languages (Tcl, Python, etc.). Strong problem-solving skills and ability to work in cross-functional teams. Eagerness to learn and improve. Excellent communication skills and attention to detail.