About this role
Design Verification Engineer at Voltai. Location: Palo Alto, California, United States. Role: Own verification, Develop AI workflows, Build reusable frameworks Requirements: 4-6 years hands-on verification; strong SystemVerilog/UVM; Python or scripting; interest in AI/automation; cross-domain collaboration; client interaction; high ownership. Category: Engineering Seniority: Mid Level Tools: SystemVerilog, UVM, Python Commitment: Full Time Workplace: Onsite Languages: English