About this role
PLL Circuit Design Engineer at TSMC - Taiwan Semiconductor Manufacturing Company Limited. Location: Yokohama, /, Japan. Role: Design PLL, Model PLL, Benchmark PLL Requirements: Master in Electrical Engineering; strong PLL theory; MATLAB modeling; spread-spectrum clocks; design experience with analog or all-digital PLLs (5+ years preferred) Category: Engineering Seniority: Mid Level Tools: MATLAB, Verilog, APR, PCB design Commitment: Full Time Workplace: Onsite Languages: English