About this role
FPGA Engineer – Intern (Australia) at Citadel Securities. Location: Sydney, New South Wales, Australia. Role: designing FPGA, testing RTL, collaborating teams Requirements: Pursuing a Bachelor's, Master's or PhD in Electrical or Computer Engineering or related field; experience with SystemVerilog or VHDL; familiarity with Python/C/Tcl/Bash; strong communication and problem-solving skills. Category: Engineering Seniority: No Prior Experience Required Tools: SystemVerilog, VHDL, Python, C, Tcl, Bash Commitment: Internship Workplace: Onsite Languages: English