About this role
Senior Digital ASIC Design Engineer at Draper. Location: Cambridge, Massachusetts, United States. Role: designing circuits, simulating circuits, optimizing hardware Requirements: Requires 5+ years ASIC hardware engineering experience, bachelor's in engineering (master's preferred), proficiency with Cadence/Synopsys flows, SystemVerilog/Verilog/VHDL, and an active US Secret clearance. Category: Engineering Seniority: Senior Level Tools: Cadence, Synopsys, System Verilog, Verilog, VHDL, LINT Commitment: Full Time Workplace: Onsite Languages: English