About this role
RTL Design Engineer at Normal Computing. Location: New York City or Palo Alto or London. Role: designing rtl, authoring verification, supporting tapeout Requirements: Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V Commitment: Full Time Workplace: Hybrid Languages: English